LT4295 datasheet(21/50 Pages) AD

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LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

Type 3 single-signature PDs request exactly one of six

possible power levels: 3.84W, 6.49W, 13W, 25.5W,

40W, or 51W.

Type 3 dual-signature PDs request exactly one of four

possible power levels on each pairset: 3.84W, 6.49W,

13W, or 25.5W. The total PD requested power is the

sum of the requested power on both pairsets.

Type 3 PD Classes overlap with Type 1 and 2 Classes in

order to provide additional Type 3 feature sets at lower

power levels.

Type 4 single-signature PDs request exactly one of two

possible power levels: 62W or 71.3W.

Type 4 dual-signature PDs request exactly 35.6W on at

least one pairset and one of five possible power levels

on the other pairset: 3.84W, 6.49W, 13W, 25.5W, or

35.6W. The total PD requested power is the sum of the

requested power on both pairsets.

Classification is extended to a possible maximum of

five class events. The additional events allow for unique

identification of existing and new PD Classes.

Type 3 and 4 PSEs issue a long first class event to

advertise Type 3 and 4 feature support to attached PDs.

Lower standby power is enabled by shortening the

length of the maintain power signature pulse (short

MPS). The PD duty cycle drops from ~23% to ~2%. A

PD is allowed to present short MPS if the PSE issues

a long first class event.

Power management is augmented by Autoclass, an

optional feature for 802.3bt PSEs and PDs. In an

Autoclass system the maximum PD power is mea-

sured and reported to the PSE host, enabling the PSE

to reclaim output power not used by the PD appli-

cation and losses in the Ethernet cabling (Table 3).

See Autoclass section and LTC9101-1 Software

Programming documentation for details.

Table 3. IEEE-Specified Power Allocations, Single-Signature PD

PD CLASS

PSE OUTPUT

POWER

ALLOCATED

CABLING LOSS

PD INPUT

POWER

0.16W

3.84W

6.7W

0.21W

6.49W

14W

13W

30W

4.5W

25.5W

45W

40W

60W

51W

75W

13W

62W

90W

18.7W

71.3W

Software register map compatibility with LTC4266,

LTC4271 and LTC4291-based PSEs has been maintained

to the extent possible. LTC4291-based PSEs utilize two

channels to control a single PSE port. LTC9101-based

PSEs can be configured to utilize either a single power

channel, delivering up to 25.5W, or as two channels,

delivering up to 71.3W.

For register map details please contact Analog Devices

to request the LTC9101-1 Software Programming

documentation.

Special Compatibility Mode Notes

As with prior generations, each I2C address provides

status and control for four PoE ports.

In 4-pair mode, each port register slice provides port

control and status as well as channel A vs B control

and status.

In 2-pair mode, each port register slice provides port

control and status via channel A control and status.

In this mode channel B control and status fields

are ignored.

Certain status registers, e.g. Port Status and Power

Status, relate to a channel state, as opposed to port

state and are split into three copies; a generalized port

state, channel A state and channel B state.

Certain command registers, e.g., Power-on pushbutton,

likewise are bifurcated to allow per-channel control.

APPLICATIONS INFORMATION

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