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Zakładka z wyszukiwarką danych komponentów |
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STM32F732IE Arkusz danych(PDF) 44 Page - STMicroelectronics |
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STM32F732IE Arkusz danych(HTML) 44 Page - STMicroelectronics |
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44 / 226 page  Functional overview STM32F732xx STM32F733xx 44/226 DS11854 Rev 6 The STM32F733xx devices feature an integrated PHY HS. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has a software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 8 bidirectional endpoints • 16 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support • Internal FS OTG PHY support • For STM32F732xx devices: External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • For STM32F733xx devices: Internal HS OTG PHY support • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal serial-bus controller on-the-go high-speed PHY controller (USBPHYC) only on STM32F733xx devices. The USB HS PHY controller: • Sets the PHYPLL1/2 values for the PHY HS. • Sets the other controls on the PHY HS. • Controls and monitors the USB PHY LDO. 3.31 Random number generator (RNG) All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.32 Advanced encryption standard hardware accelerator (AES) The devices embed an AES hardware accelerator which can be used to both encipher and decipher data using AES algorithm. The AES peripheral supports: • Encryption/Decryption using AES Rijndael Block Cipher algorithm • NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm • 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x 32-bit registers) |
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