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STM32F732IE Arkusz danych(PDF) 32 Page - STMicroelectronics

Numer części STM32F732IE
Szczegółowy opis  Arm® Cortex®-M7 32b MCUFPU, 462DMIPS, up to 512KB Flash 256164KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
PDF  226 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F732IE Arkusz danych(HTML) 32 Page - STMicroelectronics

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Functional overview
STM32F732xx STM32F733xx
32/226
DS11854 Rev 6
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor can be used to monitor the V12 of the logic power domain. The PA0 pin
can be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it is used to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset.
As a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•
The over-drive and under-drive modes are not available.
•
The Standby mode is not available.
Figure 11. Regulator OFF
The following conditions must be respected:
•
VDD must always be higher than VCAP_1 and VCAP_2 to avoid current injection between
power domains.
•
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time
for VDD to reach 1.7 V, then PA0 must be kept low to cover both conditions: until
VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V
(see Figure 12).
•
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 can be asserted low externally
(see Figure 13).
•
If VCAP_1 and VCAP_2 go below V12 minimum value, and VDD is higher than 1.7 V, then
a reset must be asserted on PA0 pin.
Note:
The minimum value of V12 depends on the maximum frequency targeted in the application.
On the LQFP64 pin package, the VCAP_2 is not available.
ai18498V3
BYPASS_REG
VCAP_1
VCAP_2
PA0
V12
VDD
NRST
VDD
Application reset
signal (optional)
External VCAP_1/2 power
supply supervisor
Ext. reset controller active
when VCAP_1/2 < Min V12
V12



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