STM32F732IE datasheet(42/226 Pages) STMICROELECTRONICS

42 / 226 page

Functional overview

STM32F732xx STM32F733xx

42/226

DS11854 Rev 6

Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They

can be operated in master or slave mode, in simplex communication modes, and can be

configured to operate with a 16-/32-bit resolution as an input or output channel. Audio

sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the

I2S interfaces is/are configured in master mode, the master clock can be output to the

external DAC/CODEC at 256 times the sampling frequency.

All I2Sx can be served by the DMA controller.

3.24

Serial audio interface (SAI)

The devices embed two serial audio interfaces.

The serial audio interface is based on two independent audio subblocks which can operate

as transmitter or receiver with their FIFO. Many audio protocols are supported by each

block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,

supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be

configured in master or in slave mode.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of

the sampling frequency.

The two subblocks can be configured in synchronous mode when full-duplex mode

is required.

SAI1 and SAI2 can be served by the DMA controller.

3.25

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows

the achievement of an error-free I2S sampling clock accuracy without compromising on the

CPU performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change

without disabling the main PLL (PLL) used for CPU and USB interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 kHz to 192 lHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

I2S/SAI flow with an external PLL (or codec output).

3.26

Audio PLL (PLLSAI)

An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is

programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz)

and the audio application requires both sampling frequencies simultaneously.

3.27

SD/SDIO/MMC card host interface (SDMMC)

SDMMC host interfaces are available, that support MultiMediaCard System Specification

Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

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