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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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SPC58ECX Arkusz danych(PDF) 62 Page - STMicroelectronics |
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SPC58ECX Arkusz danych(HTML) 62 Page - STMicroelectronics |
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62 / 153 page  Electrical characteristics SPC584Cx, SPC58ECx 62/153 DS11620 Rev 8 ΔPERREF SR T Input reference clock jitter (peak to peak) Single period, fRF_REF =20MHz —— 350 ps T Long term, fRF_REF =20MHz -500 — 500 ps ΔPEREYE CC T Output Eye Jitter (peak to peak)(5) —— — 400 ps 1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces. 2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1. 3. The 320 MHz frequency is achieved with a 20 MHz reference clock. 4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device (to set the PLL enable bit). 5. Measured at the transmitter output across a 100 Ω termination resistor on a device evaluation board. See Figure 12. Table 32. LFAST PLL electrical characteristics (continued) Symbol(1) C Parameter Conditions Value Unit Min Typ Max |
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