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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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SPC58ECX Arkusz danych(PDF) 19 Page - STMicroelectronics |
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SPC58ECX Arkusz danych(HTML) 19 Page - STMicroelectronics |
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19 / 153 page  DS11620 Rev 8 19/153 SPC584Cx, SPC58ECx Electrical characteristics 19 4.3.1 Power domains and power up/down sequencing The following table shows the constraints and relationships for the different power domains. Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as well as during normal device operation. During power-up, all functional terminals are maintained in a known state as described in the device pinout Microsoft Excel file attached to the IO_Definition document. Table 6. PRAM wait states configuration PRAMC WS Clock Frequency (MHz) 1< 180 0< 120 Table 7. Device supply relation during power-up/power-down sequence Supply2 VDD_LV VDD_HV_IO_FLEX VDD_HV_IO_MAIN VDD_HV_FLA VDD_HV_OSC VDD_HV_ADV VDD_HV_ADR VDD_HV_IO_FLEX ok not allowed ok ok VDD_HV_IO_MAIN VDD_HV_FLA VDD_HV_OSC ok ok ok ok VDD_HV_ADV ok ok not allowed ok VDD_HV_ADR ok ok not allowed not allowed |
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