NBP8 datasheet(10/58 Pages) NXP

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NXP Semiconductors

NBP8

Battery pressure monitor sensor

Clock cycle

c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16

Bit assignment

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

a12 a11 a10 a9

Write byte to

Address

Where:

c1 – c16 = SCLK cycles 1 (b15) through 16 (b0), most significant bit first, least significant bit last

b15:0 = bit assignments for each clock cycle, b15 = 0 for read; b15 = 1 for write

a12:0 = 13 LSBs of address being read or written; $0000 to $1FFF is direct; $C000 to $FFFF is indirect

p1:0 = “Even” parity bits, p1 calculated for contents of b15:9; p0 calculated for contents of b8:2

s4:0 = client status:

0 0 0 0 0 = all OK, no need for retry.

1 x x x x = reserved for future fault modes, default to 0 until defined

x 1 x x x =

the response in R0 for first T1 input after reset

in the case of commands ignored by SPI due to error in previous read command; that is, invalid data in response

in the case the write command did not execute

x x 1 x x = clock fault, not enough clocks, or too many clocks per CS_B cycle

x x x 1 x = parity fault from either p1 or p0

x x x x 1 = internal bus contention fault, SPI does not gain access to peripheral bus in the prescribed time, or attempt

access illegal or security-blocked address

d7:0 = data being read or written

t = contents of next server transmission T#+1

m = server stuff bits, 0 or 1 by server choice, and included as part of parity calculation

r = contents of previous client response R#-1

Table 5. SPI protocol architecture...continued

NBP8

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Product data sheet

Rev. 2.4 — 11 March 2022

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NBP8 Arkusz danych(PDF) 10 Page - NXP Semiconductors