SMM665B datasheet(4/30 Pages) SUMMIT

4 / 30 page

SMM665B

Preliminary Information

Summit Microelectronics, Inc

2089 1.1 10/20/04

Number

Type

Pin Name

Pin Description

DATA

SDA

2C Bi-directional data line

CLK

SCL

2C Clock line

The address pin is biased either to VDD_CAP or GND.

When

communicating with the SMM665B over the 2-wire bus A2 provides a

mechanism for assigning a unique bus address.

Programmable active high/low input. When asserted the RST output will be

go active. When de-asserted the RST output will go inactive immediately

after a reset timeout period (tPRTO) if there are no RST trigger sources active.

This timeout period makes it suitable to use a pushbutton for manual reset.

PWR_ON/OFF

Programmable active high/low input signals the start of the power

sequencing. When asserted the part will sequence the supplies on and

when de-asserted the part will sequence the supplies off.

Note: The SMM665B does not monitor for faults during sequencing. The

PWR_ON/OFF pin is overridden by the I

2C power on/off command. To get

the pin to work again requires the part be given an I

2C 'Clear' command (see

page 16, “RESTART OF POWER-ON CASCADE SEQUENCING”).

Programmable active high/low input. Force shutdown is used to immediately

turn off all converter enable signals (PUP outputs) when a fault is detected.

OUT

FAULT

Programmable active high/low open drain Fault output.

Active when a

programmed fault condition exists on AIN1, AIN2, or the internal temperature

sensor.

OUT

HEALTHY

Programmable active high/low open drain Healthy output. Active when all

programmed power supply inputs and monitored inputs are within OV and

UV limits.

OUT

RST

Programmable active high/low open drain Reset output. Active when a

programmed fault condition exists on any power supply inputs or monitored

inputs or when MR is active. RST has a programmable timeout period with

options for 0.64ms, 25ms, 100ms and 200ms.

AIN1

General purpose monitored analog input

AIN2

General purpose monitored analog input

GND

Ground

VREF_ADC

Voltage reference input used for A/D conversion where:

(4XVREF_ADC) = Full Scale (FS) for VMA-F and VDD

(12XVREF_ADC) = FS for 12VIN

(2XVREF_ADC) = FS for AIN1 and AIN2.

VREF_ADC can be connected to VREF_CNTL in most applications.

PIN DESCRIPTIONS

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