PS10/PS11

3

A051204

PWRGD Logic

Model

Condition

PWRGD-A/B/C/D

INACTIVE (not ready)

0

PS10

ACTIVE (Ready)

1

HI Z

INACTIVE (not ready)

1

HI Z

PS11

ACTIVE (Ready)

0

Pinout

2

1

3

4

5

6

7

12

13

14

9

8

11

10

PWRGD-C (PS10)

PWRGD-C (PS11)

PWRGD-B (PS11)

PWRGD-B (PS10)

PWRGD-A (PS11)

PWRGD-A (PS10)

PWRGD-D (PS11)

PWRGD-D (PS10)

NC

V

UV

OV

V

TD

TC

RAMP

NC

TB

EE

IN

Top View

Pin Description

PWRGD-D – This open drain Power Good Output Pin is

held inactive on initial power application and goes active a

programmed time delay after PWRGD-C goes active.

PWRGD-C – This open drain Power Good Output Pin is

held inactive on initial power application and goes active a

programmed time delay after PWRGD-B goes active.

PWRGD-B – This open drain Power Good Output Pin is

held inactive on initial power application and goes active a

programmed time delay after PWRGD-A goes active.

PWRGD-A – This open drain Power Good Output Pin is

held inactive on initial power application and goes active one

POR delay after the UV pin goes above its High threshold

period).

To function as an indicator a pullup resistor must be con-

nected from this pin to a voltage rail no more than 90V from

OV – This Over Voltage (OV) sense pin, when raised above

its high threshold will immediately cause the Power Good

Outputs to be pulled low. These outputs will remain low until

the voltage on this pin falls below the low threshold limit,

initiating a new start-up cycle.

UV – This Under Voltage (UV) sense pin, when lowered

below its low threshold will immediately cause the Power

Good Outputs to be pulled low. These outputs will remain

low until the voltage on this pin rises above the low thresh-

old limit, initiating a new start-up cycle.

input to the circuit.

input to the circuit and can withstand 90V with respect to

time delay from PWRGD-C going active to PWRGD-D going

active.

time delay from PWRGD-B going active to PWRGD-C going

active.

time delay from PWRGD-A going active to PWRGD-B going

active.

RAMP – This pin provides a current output so that a timing

ramp is generated when a capacitor is connected. This tim-

ing Ramp is used to program POR and the time from satis-

faction of the UV/OV supervisors to PWRGD-A.

NC– No Connect. This pin can be grounded or left floating.