PS10/PS11

4

A051204

Functional Block Diagram

Logic

Regulator

& POR

+

UVLO

Vbg

UV

-

V

V

Band Gap

Reference

Programmable

Timer

TD

PWRGD-B

PWRGD-A

PWRGD-C

PWRGD-D

TC

TB

Vint

10uA

Vint

RAMP

+

-

OV

Vint - 1.2V

EE

IN

Functional Description

The PS10/PS11 are designed to sequence up to 4 power

supply modules, ICs or subsystems when the backplane

voltage is within the programmed Under-voltage and Over-

voltage limits. The power good open drain outputs are

sequentially enabled starting from PWRGD-A to PWRGD-

D. The time delay between power goods is programmable

up to 200ms simply by changing the value(s) of RTB,

RTC, and RTD. The initial time between satisfaction of the

UV/OV supervisors & PWRGD-A can be programmed with

Cramp.

Description of Operation

During the initial power application, the Power Good pins

PS11. Once the internal under voltage lock out has been

satisfied, the circuit checks the input supply under voltage

(UV) and over voltage (OV) sense circuits to ensure that

the input voltage is within programmed limits. These limits

are determined by the selected values for R1, R2, and R3,

which form a voltage divider.

At the same time, a 10

µA current source is enabled,

charging the external capacitor connected to the ramp pin.

The rise time of the ramp pin is determined by the value of

the capacitor (10

µA/Cramp). When the ramp voltage

reaches 8.8V, the PWRGD-A pin will change into an active

state. PWRGD-B will change into an active state after a

programmed time delay from PWRGD-A inactive to active

transition. PWRGD-C will change into an active state after

a programmed time delay from PWRGD-B inactive to ac-

tive transition. PWRGD-D will change into an active state

after a programmed time delay from PWRGD-C inactive to

active transition.

The controller continuously monitors the UV and OV pins

as long as the internal UVLO and POR circuits are satis-

fied. At any time during the start up cycle or thereafter,

crossing the UV low and OV high limits will cause an im-

mediate discharge on Cramp and reset on the power good

pins. When the input voltage returns to a value within the

programmed UV and OV limits, a new start up sequence

will initiate immediately.

Programming the Under and Over Voltage Limits

The UV and OV pins are connected to comparators with

nominal 1.17V thresholds and 100mV of hysteresis (1.17V

± 50mV). They are used to detect under voltage and over

voltage conditions at the input to the circuit. Whenever the

OV pin rises above its high threshold (1.22V) or the UV pin

falls below its low threshold (1.12V), the PWRGD outputs

immediately deactivate.

Calculations can be based on either the desired input volt-

age operating limits or the input voltage shutdown limits. In

the following equations the shutdown limits are assumed.

The undervoltage and overvoltage shut down thresholds

can be programmed by means of the three resistor divider

formed by R1, R2 and R3. Since the input currents on the

UV and OV pins are negligible the resistor values may be

calculated as follows: