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RA4M2 Arkusz danych(PDF) 47 Page - Renesas Technology Corp

Numer części RA4M2
Szczegółowy opis  Leading-performance 100 MHz Arm Cortex-M33 core, up to 512 KB code flash memory with background operation, 8 KB Data flash memory, and 128 KB SRAM with Parity/ECC.
PDF  92 Pages
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Producent  RENESAS [Renesas Technology Corp]
Strona internetowa  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RA4M2 Arkusz danych(HTML) 47 Page - Renesas Technology Corp

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tDr, tDf
tSA
tOH
tLEAD
tTD
tLAG
tH
LSB OUT
(Last data)
DATA
MSB OUT
MSB IN
DATA
LSB IN
MSB IN
LSB OUT
tSU
tOD
tREL
MSB OUT
SSn
input
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
MISOn
output
MOSIn
input
Note:
n = 0 to 4, 9
Figure 2.32
SCI simple SPI mode timing for slave when CKPH = 0
Table 2.26
SCI timing (3)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Max
Unit
Test conditions
Simple IIC
(Standard mode)
SDA input rise time
tSr
—
1000
ns
Figure 2.33
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb*1
—
400
pF
Simple IIC
(Fast mode)
SDA input rise time
tSr
—
300
ns
Figure 2.33
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb*1
—
400
pF
Note:
tIICcyc: IIC internal reference clock (IICφ) cycle.
Note 1. Cb indicates the total capacity of the bus line.
RA4M2 Datasheet
2. Electrical Characteristics
R01DS0367EJ0110 Rev.1.10
Jan 27, 2021
Page 47 of 92



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