PACDN009 datasheet(6/8 Pages) CALMIRCO

6 / 8 page

430 N. McCarthy Blvd., Milpitas, CA 95035-5112

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Tel: 408.263.3214

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Fax: 408.263.7846

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www.calmicro.com

09/21/04

PACDN009

Application Information (cont’d)

Implementation Examples

ESD events are very high-speed pulses with rise times

in the range of 1ns or less. To effectively use the

PACDN009, the following design guidelines must be

observed (as discussed in the application section):

1) The inductance from the VN and VP connections of

the PACDN009 to ground must be very low. This

includes the path through the VP decoupling capacitor

to ground and the path to the power supply (as dis-

cussed above).

2) The inductance between the connector pin to be

protected and the PACDN009 channel input pin must

be kept to a minimum. If there is a large inductance

here, the ESD event will find a lower impedance path

which will more likely be through the device to be pro-

tected. Figure 2 shows the implementation schematic

and Figure 3 shows a possible layout for the

PACDN009. In figure 3, notice the large VCC and

ground areas with multiple via connections to the

underlying reference planes and the positioning of the

bypass capacitor. Note how the signal lines to be pro-

tected flow from the connector to the PACDN009 and

then out to the device to be protected (Figure 3). This

daisy chaining provides a low impedance path from the

connector to the PACDN009 and a higher impedance

path from the PACDN009 to the protected device.

Figure 2. Typical ESD protection implementation

ONE

CHANNEL

PAC DN009

GROUND RAIL

POSITIVE SUPPLY RAIL

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

POWER SUPPLY

OPTIONAL

ZENER DIODE

FOR EXTRA

PROTECTION

CHANNEL

INPUT

DECOUPLING

CAPCITOR

0.22

µF

LINE BEING

PROTECTED

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