Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

Preview PDF HTML

INA232 Arkusz danych(PDF) 7 Page - Texas Instruments

Numer części INA232
Szczegółowy opis  INA232 48-V, 16-Bit, Current, Voltage, and Power Monitor With an I2C Interface
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

INA232 Arkusz danych(HTML) 7 Page - Texas Instruments

Back Button INA232 Datasheet HTML 3Page - Texas Instruments INA232 Datasheet HTML 4Page - Texas Instruments INA232 Datasheet HTML 5Page - Texas Instruments INA232 Datasheet HTML 6Page - Texas Instruments INA232 Datasheet HTML 7Page - Texas Instruments INA232 Datasheet HTML 8Page - Texas Instruments INA232 Datasheet HTML 9Page - Texas Instruments INA232 Datasheet HTML 10Page - Texas Instruments INA232 Datasheet HTML 11Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 32 page
background image
6.6 Timing Requirements (I2C)
MIN
NOM
MAX
UNIT
I2C BUS (FAST MODE)
F(SCL)
I2C clock frequency
1
400
kHz
t(BUF)
Bus free time between STOP and START conditions
600
ns
t(HDSTA)
Hold time after a repeated START condition. After this period, the first
clock is generated.
100
ns
t(SUSTA)
Repeated START condition setup time
100
ns
t(SUSTO)
STOP condition setup time
100
ns
t(HDDAT)
Data hold time
10
900
ns
t(SUDAT)
Data setup time
100
ns
t(LOW)
SCL clock low period
1300
ns
t(HIGH)
SCL clock high period
600
ns
tF
Data fall time
300
ns
tF
Clock fall time
300
ns
tR
Clock rise time
300
ns
tR
Clock rise time (SCLK ≤ 100 kHz)
1000
ns
I2C BUS (HIGH-SPEED MODE)
F(SCL)
I2C clock frequency
10
2940
kHz
t(BUF)
Bus free time between STOP and START conditions
160
ns
t(HDSTA)
Hold time after a repeated START condition. After this period, the first
clock is generated.
100
ns
t(SUSTA)
Repeated START condition setup time
100
ns
t(SUSTO)
STOP condition setup time
100
ns
t(HDDAT)
Data hold time
10
125
ns
t(SUDAT)
Data setup time
20
ns
t(LOW)
SCL clock low period
200
ns
t(HIGH)
SCL clock high period
60
ns
tF
Data fall time
80
ns
tF
Clock fall time
40
ns
tR
Clock rise time
40
ns
6.7 Timing Diagram
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
t
(BUF)
S
S
P
P
Figure 6-1. I2C Timing Diagram
www.ti.com
INA232
SBOSAA2 – DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: INA232



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Arkusz danych Pobierz

Go To PDF Page


Link URL



Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Link do karty katalogowej    |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com