7.6 Register Maps

7.6.1 Device Registers

Table 7-2 lists the INA232 registers. All register locations not listed in Table 7-2 should be considered as

reserved locations and the register contents should not be modified.

Table 7-2. INA232 Registers

Address

Register Name

Register Size (bits)

Reset Value

Section

0h

Configuration Register

16

4127h

Go

1h

Shunt Voltage Register

16

0000h

Go

2h

Bus Voltage Register

16

0000h

Go

3h

Power Register

16

0000h

Go

4h

Current Register

16

0000h

Go

5h

Calibration Register

16

0000h

Go

6h

Mask/Enable Register

16

0000h

Go

7h

Alert Limit Register

16

0000h

Go

3Eh

Manufacturer ID Register

16

5449h

Go

Complex bit access types are encoded to fit into small table cells. Table 7-3 shows the codes that are used for

access types in this section.

Table 7-3. Device Access Type Codes

Access Type

Code

Description

Read Type

R

R

Read

Write Type

W

W

Write

7.6.1.1 Configuration Register (Address = 0h) [reset = 4127h]

The configuration register is shown in Table 7-4.

Table 7-4. Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

15

RST

R/W

0b

Set this bit to '1' to generate a system reset that is the same as power-

on reset.

Resets all registers to default values and then self-clears.

0b = Normal Operation

1b = System Reset self clears registers to default values

14-13

Reserved

R

10b

Reserved value always returns 10b

12

ADCRANGE

R/W

0b

Enables the selection of the shunt full scale input across IN+ and IN–.

0b = ±81.92 mV

1b = ±20.48 mV

11-9

AVG

R/W

000b

Sets the number of ADC conversion results to be averaged. The read-

back registers are updated after averaging is completed.

000b = 1

001b = 4

010b = 16

011b = 64

100b = 128

101b = 256

110b = 512

111b = 1024

INA232

SBOSAA2 – DECEMBER 2022

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