Frame 1 Two-Wire Target Address Byte

(1)

Frame 2 Register Pointer Byte

1

Start By

Controller

ACK By

Target

ACK By

Target

1

9

1

9

SDA

SCL

0

0

A3

A2

A1

A0

R/W

P7

P6

P5

P4

P3

P2

P1

P0

Stop

A.

The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 7-1.

Figure 7-5. Typical Register Pointer Set

7.5.3 High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The controller

generates a start condition followed by a valid serial byte containing high-speed (HS) controller code 00001XXX.

This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The

device does not acknowledge the HS controller code, but does recognize it and switches its internal filters to

support 2.94-MHz operation.

The controller then generates a repeated start condition (a repeated start condition has the same timing as

the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start conditions

to maintain the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the

device to support the F/S mode.

7.5.4 General Call Reset

A general call reset to multiple devices is implemented by addressing the general call address 0000 000, with

the last R/W bit set to 0. This is then followed by the following data byte 0000 0110 (06h).

On receiving this 2-byte sequence, all devices designed to respond to the general call address will reset. All

INA232 devices on the bus will do a soft reset operation and return to the default power-up conditions

7.5.5 General Call Start Byte

A general call ADC conversion start command to multiple INA232 devices is implemented by addressing the

general call address 0000 000, with the last R/W bit set to 1. No other data bytes are required. Be aware that

other devices in the bus that use general call start commands on the bus will also trigger a start of conversion.

7.5.6 SMBus Alert Response

The INA232 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response provides

a quick fault identification for simple targets. When an Alert occurs, the controller can broadcast the Alert

Response target address (0001 100) with the Read/Write bit set high. Following this Alert Response, any target

that generates an alert identifies itself by acknowledging the Alert Response and sending its address on the bus.

The Alert Response can activate several different target devices simultaneously, similar to the I2C General Call.

If more than one target attempts to respond, bus arbitration rules apply. The losing device does not generate an

Acknowledge and continues to hold the Alert line low until that device wins arbitration.

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INA232

SBOSAA2 – DECEMBER 2022

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