In the case of a register write command, the TPM reads on the SPI_MOSI pin the number of bytes previously

declared and modifies accordingly the TPM state machine.

Table 2. SPI bit protocol

Bit transfer order on

SPI_MISO/SPI_MOSI pins

Byte on SPI_MISO/SPI_MOSI

pins

Usage

Notes

RFU

67 for 64B transactions

11 for 8B transactions

future use for larger register sizes

-

57-63 – last bits on wire

7

Data[30:24]

-

56

Data[31]

msb of 4th LSB

49-55

6

Data[22:16]

-

48

Data[23]

msb of 3rd LSB

41-47

5

Data[14:8]

-

40

Data[15]

msb of 2nd LSB

33-39

4

Data[6:0]

-

32

Data[7]

msb of 1st LSB

Optional flow control can be done in this window. See Section 3.1.2 Protocol flow control for SPI read access and Section 3.1.3 Protocol flow

control for SPI write access for details. This is the only place in the bit transfers where flow control can be performed.

31

3

Addr[0]

lsb of address

9-30

1-3

Addr[22] down to Addr[1]

-

8

1

Addr[23]

msb of address

2-7

0

bits[5:0]

Size of transfer

where bit[5] of this field is the 3rd bit

transferred on the wire, and bit [0] is the 8th

bit on the wire. This field is 0’s based count

of the bytes. Any byte count from 1 to 64 is

legal.

Bit [5:0] decode

‘11_1111’ = 64 bytes

‘

etc. for 63 down to 6 bytes

‘00_0100’ = 5 bytes

‘00_0011’ = 4 bytes

‘00_0010’ = 3 bytes

‘00_0001’ = 2 bytes

‘00_0000’ = 1 byte

1

Reserved; bit[6]

-

0 – first bit on wire

Byte0, bit[7] Read/Write

1=read, 0 = write

3.1.2

Protocol flow control for SPI read access

Following the standard specification, depending on the targeted register, the TPM is authorized to insert 1 Wait

state before acknowledging the read access. A Wait state is a Low state (0) sent on the SPI_MISO pin by the

TPM. An Acknowledgment is a byte, whose last bit is ‘1’, sent on the SPI_MISO pin by the TPM.

The ST TPM uses only one wait state for SPI read access.

On read access, if the data are not available, the ST TPM uses the dedicated bits defined by the standard

specification:

•

stsValid (bit 7 in the Status register): This bit indicates whether TPM_STS_x.dataAvail and

TPM_STS_x.Expect are valid. They are valid when stsValid = 1.

•

tpmRegValidSts (bit 7 in the Access register): This bit indicates whether all other bits in this register contain

valid values. All values are valid when tpmRegValidSts = 1.

The Host should repeat read access and consider that the TPM is out of order only after TIMEOUT_B (2 seconds)

of no data availability.

ST33TPHF2XSPI

SPI communication protocol flow control

DS14186 - Rev 1

page 6/35