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ST33TPHF2XSPI Arkusz danych(PDF) 8 Page - STMicroelectronics

Numer części ST33TPHF2XSPI
Szczegółowy opis  STSAFE-TPM ST33TPHF2XSPI: TPM 2.0 device with an SPI interface
PDF  35 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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3.2.1
FIFO interface
Table 3. List of FIFO register space addresses
Locality 0
Register name
Locality
1
Register name
Locality
2
Register name
Locality 3
Register name
Locality
4
Register name
Register description
0x0000
TPM_ACCESS_0
0x1000
TPM_ACCESS_1
0x2000
TPM_ACCESS_2
0x3000
TPM_ACCESS_3
0x4000
TPM_ACCESS_4
Used to gain ownership of the
TPM for this particular Locality
0x000B-
0x0008
TPM_INT_
ENABLE_0
0x100B-
0x1008
TPM_INT_
ENABLE_1
0x200B-
0x2008
TPM_INT_
ENABLE_2
0x300B-
0x30008
TPM_INT_
ENABLE_3
0x400B-
0x4008
TPM_INT_
ENABLE_4
Interrupt Configuration Register
0x000C
TPM_INT_
VECTOR_0
0x100C
TPM_INT_
VECTOR_1
0x200C
TPM_INT_
VECTOR_2
0x300C
TPM_INT_
VECTOR_3
0x400C
TPM_INT_
VECTOR_4
SIRQ vector to be used by the
TPM (SIRQ pin not available)
0x0013-
0x0010
TPM_INT_
STATUS_0
0x1013-
0x1010
TPM_INT_
STATUS_1
0x2013-
0x2010
TPM_INT_
STATUS_2
0x3013-
0x3010
TPM_INT_
STATUS_3
0x4013-
0x4010
TPM_INT_
STATUS_4
Shows which interrupt has
occurred
0x0017-
0x0014
TPM_INTF_
CAPABILITY_0
0x1017-
0x1014
TPM_INTF_
CAPABILITY_1
0x2017-
0x2014
TPM_INTF_
CAPABILITY_2
0x3017-
0x3014
TPM_INTF_
CAPABILITY_3
0x4017-
0x4014
TPM_INTF_
CAPABILITY_4
Provides the information about
supported interrupts and the
characteristic of the burstCount
register of the particular TPM.
0x001A-
0x0018
TPM_STS_0
0x101A-
0x1018
TPM_STS_1
0x201A-
0x2018
TPM_STS_2
0x301A-
0x3018
TPM_STS_3
0x401A-
0x4018
TPM_STS_4
Status Register. Provides status
of the TPM
-
-
-
-
-
-
-
-
0x4020
TPM_HASH_END
This signals the end of the hash
operation in Locality 4.
0x00027-
0x0024
TPM_DATA_
FIFO_0
0x1027-
0x1024
TPM_DATA_
FIFO_1
0x2027-
0x2024
TPM_DATA_
FIFO_2
0x3027-
0x3024
TPM_DATA_
FIFO_3
0x4027-
0x4024
TPM_HASH_DATA /
TPM_DATA_FIFO_4
ReadFIFO or WriteFIFO,
depending on the current bus
cycle (read or write).
These four addresses are
aliased to one inside the TPM. In
Locality 4, it is the HASH_DATA
FIFO.
-
-
-
-
-
-
-
-
0x4028
TPM_HASH_START
This signals the start of the hash
operation in Locality 4.
0x0080-
0x0083
TPM_XDATA_
FIFO_0
0x1080-
0x1083
TPM_XDATA_
FIFO_1
0x2080-
0x2083
TPM_XDATA_
FIFO_2
0x3080-
0x3083
TPM_XDATA_
FIFO_3
0x4080-
0x4083
TPM_XDATA_
FIFO_4
Extended ReadFIFO or
WriteFIFO, depending on the
current bus cycle (read or write).
Transactions to this address
may be any size from 1B to
maxTransferCapability identified
in the capability register.
0x00BF-
0x0084
Reserved
0x10BF-
0x1084
Reserved
0x20BF-
0x2084
Reserved
0x30BF-
0x3084
Reserved
0x40BF-
0x4084
Reserved
-
0x0F03-
0x0F00
TPM_DID_VID_0
0x1F03-
0x1F00
TPM_DID_VID_1
0x2F03-
0x2F00
TPM_DID_VID_2
0x3F03-
0x3F00
TPM_DID_VID_3
0x4F03-
0x4F00
TPM_DID_VID_4
Vendor and device ID
0x0F04
TPM_RID_0
0x1F04
TPM_RID_1
0x2F04
TPM_RID_2
0x3F04
TPM_RID_3
0x4F04
TPM_RID_4
Revision ID
0x0F7F-
0x0F05
Reserved
0x1F7F-
0x1F05
Reserved
0x2F7F-
0x2F05
Reserved
0x3F7F-
0x3F05
Reserved
0x4F7F-
0x4F05
Reserved
-



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