DA7400 datasheet(5/133 Pages) RENESAS

5 / 133 page

DA7400

High Performance Stereo Codec

Final

Datasheet

Revision 3.1

28-Dec-2021

CFR0011-120-00

5 of 132

15.3.1

Selecting the PLL Input Clock ............................................................................. 59

15.3.2

Configuring the Input Divider ............................................................................... 59

15.3.3

Programming the Feedback Divider .................................................................... 59

15.3.4

Enabling Sample Rate Matching ......................................................................... 59

15.3.5

PLL Status Monitoring ......................................................................................... 59

15.3.6

PLL Calculation Example .................................................................................... 59

15.4 Audio Processing Unit......................................................................................................... 60

15.4.1

APU Gain Control ................................................................................................ 60

15.4.2

Reading and Writing Memories ........................................................................... 60

15.4.3

DSP Input Selection............................................................................................. 61

15.4.4

DSP Status Monitoring ........................................................................................ 61

15.4.5

DSP Programs..................................................................................................... 61

15.5 Input Path ............................................................................................................................ 61

15.5.1

Input Filters Selection .......................................................................................... 61

15.5.2

Gain Control......................................................................................................... 61

15.5.3

High-Pass Filter ................................................................................................... 61

15.5.4

Automatic Level Control Setup ............................................................................ 61

15.5.5

Level Detect......................................................................................................... 62

15.6 Output Path ......................................................................................................................... 63

15.6.1

Fixed Gain ........................................................................................................... 63

15.6.2

High-Pass Filter ................................................................................................... 63

15.6.3

Headphone Charge Pump ................................................................................... 63

15.7 Digital Audio Interface ......................................................................................................... 63

15.7.1

Configuring the DAI ............................................................................................. 63

15.7.1.1

Master/Slave Mode.......................................................................... 63

15.7.1.2

Slot Count ........................................................................................ 63

15.7.1.3

Data Format..................................................................................... 63

15.7.1.4

Frame Length .................................................................................. 64

15.7.1.5

Word Length .................................................................................... 64

15.7.1.6

Data Control..................................................................................... 64

15.7.1.7

Offset ............................................................................................... 64

15.7.2

DAI Channel Selection......................................................................................... 64

15.7.3

Sample Rate Converter ....................................................................................... 65

15.8 Digital Microphone Interface Programming......................................................................... 65

15.8.1

DMIC Input Enable .............................................................................................. 65

15.9 DMIC Clock Frequency Selection ....................................................................................... 65

15.9.1

DMIC Data Sampling Point.................................................................................. 65

15.9.2

DMIC Router Configuration ................................................................................. 65

15.10 Signal Generator ................................................................................................................. 66

15.10.1 Tone Generator ................................................................................................... 66

15.10.1.1

Sine Wave Generator Frequency Selection .................................... 66

15.10.1.2

DC Output........................................................................................ 66

15.10.1.3

Gain ................................................................................................. 66

15.10.1.4

Enabling and Disabling the Tone Generator ................................... 66

15.10.2 Noise Generator .................................................................................................. 66

15.10.2.1

Seed Programming.......................................................................... 66

15.10.2.2

Polynomial Programming ................................................................ 66

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