DA7400 datasheet(7/133 Pages) RENESAS

7 / 133 page

DA7400

High Performance Stereo Codec

Final

Datasheet

Revision 3.1

28-Dec-2021

CFR0011-120-00

7 of 132

16.2.13.4

PRBS Enable................................................................................. 119

16.2.14 Sine Wave Signal Generator ............................................................................. 119

16.2.14.1

Tone Generator Configuration....................................................... 119

16.2.15 Analog Peripherals ............................................................................................ 121

16.2.15.1

Temperature Interrupt Handling .................................................... 121

16.2.15.2

Pad Configuration .......................................................................... 122

16.2.16 APU.................................................................................................................... 123

16.2.16.1

PROG-0 SRAM.............................................................................. 123

16.2.16.2

PROG-1 SRAM.............................................................................. 123

16.2.16.3

DATA SRAM.................................................................................. 123

16.2.16.4

Mailbox SRAM Access .................................................................. 123

16.2.16.5

DSP Input Source Selection .......................................................... 125

16.2.16.6

DSP Gain....................................................................................... 126

17 Package Information ................................................................................................................. 128

17.1 WLCSP32 Package Outline .............................................................................................. 128

17.2 Moisture Sensitivity Level (MSL)....................................................................................... 129

17.3 WLCSP Handling .............................................................................................................. 129

17.4 Soldering Information ........................................................................................................ 129

18 Ordering Information ................................................................................................................ 130

19 Application Information ............................................................................................................ 130

20 Layout Guidelines ..................................................................................................................... 131

20.1 WLCSP ............................................................................................................................. 131

Figures

Figure 1: System Diagram..................................................................................................................... 1

Figure 2: Block Diagram ...................................................................................................................... 13

Figure 3: WLCSP Pinout Diagram (Top View) .................................................................................... 15

Figure 4: References Block Diagram .................................................................................................. 28

Figure 5: I2C Control Interface Bus...................................................................................................... 29

Figure 6: I2C Start and Stop Conditions .............................................................................................. 30

Figure 7: I2C Byte Write (SDA line) ..................................................................................................... 30

Figure 8: I2C Page Write (SDA line) .................................................................................................... 30

Figure 9: Examples of the I2C Byte Read (SDA line) .......................................................................... 31

Figure 10: Examples of I2C Page Read (SDA line) ............................................................................. 31

Figure 11: System Sequencer ............................................................................................................. 32

Figure 12: Clocking Block Diagram ..................................................................................................... 34

Figure 13: PLL Block Diagram ............................................................................................................ 35

Figure 14: Clock Generator Block Diagram......................................................................................... 37

Figure 15: APU Block Dependencies .................................................................................................. 38

Figure 16: APU Signal Path Diagram.................................................................................................. 39

Figure 17: DSP Connections ............................................................................................................... 41

Figure 18: Input Path Block Diagram .................................................................................................. 42

Figure 19: Analog Microphone Connection ......................................................................................... 43

Figure 20: ALC Operation and Parameters......................................................................................... 44

Figure 21: Output Path Block Diagram................................................................................................ 45

Figure 22: DAI Block Diagram ............................................................................................................. 47

Figure 23: Master Mode ...................................................................................................................... 48

Figure 24: Slave Mode ........................................................................................................................ 48

Figure 25: I2S Format .......................................................................................................................... 49

Figure 26: DSP Format........................................................................................................................ 49

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