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DA7400

High Performance Stereo Codec

Final

Datasheet

Revision 3.1

28-Dec-2021

CFR0011-120-00

11 of 132

Table 157: APU_PROG_RAM1_END (0x4FFF) ............................................................................... 123

Table 158: APU_DATA_RAM_START (0x5000) .............................................................................. 123

Table 159: APU_DATA_RAM_END (0x57FF) .................................................................................. 123

Table 160: APU_ADDR_B0 (0x6000) ............................................................................................... 123

Table 161: APU_ADDR_B1 (0x6001) ............................................................................................... 123

Table 162: APU_WDATA_B0 (0x6002) ............................................................................................ 124

Table 163: APU_WDATA_B1 (0x6003) ............................................................................................ 124

Table 164: APU_WDATA_B2 (0x6004) ............................................................................................ 124

Table 165: APU_WDATA_B3 (0x6005) ............................................................................................ 124

Table 166: APU_RDATA_B0 (0x6006) ............................................................................................. 124

Table 167: APU_RDATA_B1 (0x6007) ............................................................................................. 124

Table 168: APU_RDATA_B2 (0x6008) ............................................................................................. 124

Table 169: APU_RDATA_B3 (0x6009) ............................................................................................. 124

Table 170: APU_RT (0x600A)........................................................................................................... 124

Table 171: APU_WT (0x600B) .......................................................................................................... 125

Table 172: APU_FF_MXDSP_C0_SEL (0x6024) ............................................................................. 125

Table 173: APU_FF_MXDSP_C1_SEL (0x6025) ............................................................................. 125

Table 174: APU_FB_MXDSP_C0_SEL (0x6026) ............................................................................. 125

Table 175: APU_FB_MXDSP_C1_SEL (0x6027) ............................................................................. 125

Table 176: APU_USER_GAIN_C0_DB (0x6028) ............................................................................. 126

Table 177: APU_USER_GAIN_C0_FINE (0x6029) .......................................................................... 126

Table 178: APU_USER_GAIN_C1_DB (0x602A)............................................................................. 126

Table 179: APU_USER_GAIN_C1_FINE (0x602B).......................................................................... 126

Table 180: APU_GAIN_RATE (0x602C)........................................................................................... 127

Table 181: Ordering Information ....................................................................................................... 130

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