5 of 49

January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

7 Interfaces Overview

Figure 3 Interface Diagram

sRIO Ports

The sRIO interfaces are the main communication ports on the switch. These ports are compliant with the serial RapidIO v. 1.3 specifications. Please

refer to the serial RapidIO specifications for full detail [2-10].

The CPS-10Q provides 40 differential dual simplex transceivers dedicated to sRIO I/O. In addition to standard quads that act as a single 1x or 4x port,

two enhanced quads can be independently configured to run in various configurations as 4 1x-ports or 1 4x-ports. The device supports a maximum of

16 1x-ports, or 10 4x-ports. Each port can be programmed to run independently at 1.25, 2.5, or 3.125Gbps. Each lane is able to handle long- or short-

haul serial transmission per RIO serial spec.

In the CPS-10Q there are 8 “Standard Quads” which follow the standard sRIO physical interface implementation. These ports either operate in 4x-

mode or as a single 1x-port. For example Lanes 0 - 3 are programmable into one 4x- or one 1x-port. Per sRIO standard, either the 1st or 3rd lanes in

a given 4x group may be used as a valid link for a 1x port. For example, either lane 0 or lane 2 may be connected in support of a 1x-port.

The CPS-10Q also has a proprietary implementation which we refer to as an “Enhanced Quad” for Quad4 and Quad9. An Enhanced Quad can be

operated in standard sRIO mode like the standard quads. Additionally the Enhanced Quad can be register-configured to run as 4 independent 1x-

ports. In this manner, the user has the flexibility to use one, multiple, or two lanes in 1x-mode. For example, lanes 16 - 19 of the CPS-10Q are

programmable into one 4x- or four 1x-ports. This is unlike the standard sRIO port implementation that, when configured as a 1x-port, renders the

remaining possible connections unused.

I2C Bus

This interface may be used as an alternative to the standard sRIO or JTAG ports to program the switch and to check the status of registers - including

the error reporting registers. It is fully compliant with the I2C specification, it supports master mode and slave mode, also supports both Fast- and

Slow-mode buses [1]. Refer to the “I2C” section for full detail.

JTAG TAP Port

This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [10, 11]. It may also be used as an alternative to the standard sRIO or I2C

ports to program the switch and to check the status of registers - including the error reporting registers. It has 5 pins. Refer to the JTAG chapter for full

detail.

IDT CPS-10Q

40

Differential

sRIO Lanes

1.25, 2.5, or

3.125 Gbps

I2C

Interface

400KHz

RST

REF_CLK

IRQ

Rext

SPD[1:0]