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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

Interrupt (IRQ)

An interrupt output is provided in support of Error Management functionality. This output may be used to flag a host processor in the event of error

conditions within the device. Refer to the Error Handling chapter for full detail.

Reset

A single Reset pin is used for full reset of the CPS-10Q, including setting all registers to power-up defaults. Refer to the Reset & Initialization chapter

for full detail.

Clock

The single system clock (REF_CLK+ / -) is a 156.25MHz differential clock.

Rext (Rextn & Rextp)

These pins are used to establish the drive bias on the SerDes output. An external bias resistor is required. The two pins must be connected to one

another with a 12k Ohm resistor. This provides CML driver stability across process and temperature.

SPD[1:0]

Speed Select Pins. These pins define the sRIO port speed at RESET for all ports. The RESET setting may be overridden by subsequent programming

of the QUAD_CTRL register. SPD[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins must remain STATICALLY BIASED after

power-up.