MPC8560CPXAPDB datasheet(54/108 Pages) FREESCALE

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

I2C

11 I2C

This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8560.

11.1 I2C DC Electrical Characteristics

Table 39 provides the DC electrical characteristics for the I2C interface of the MPC8560.

11.2 I2C AC Electrical Specifications

Table 40 provides the AC timing parameters for the I2C interface of the MPC8560.

Table 39. I2C DC Electrical Characteristics

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

VIH

0.7

× OVDD

OVDD+ 0.3

Input low voltage level

VIL

–0.3

0.3

× OVDD

Low level output voltage

VOL

0.2

× OVDD

Pulse width of spikes which must be suppressed

by the input filter

tI2KHKL

Input current each I/O pin (input voltage is

between 0.1

× OVDD and 0.9 × OVDD(max)

–10

µA

Capacitance for each I/O pin

—

Notes:

1.Output voltage (open drain or open collector) condition = 3 mA sink current.

2.Refer to the MPC8560 PowerQUICC III Integrated Communications Processor Preliminary Reference Manual for

information on the digital filter used.

3.I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.

Table 40. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Table 39).

Parameter

Symbol 1

Min

Max

Unit

SCL clock frequency

fI2C

400

kHz

Low period of the SCL clock

tI2CL

1.3

—

µs

High period of the SCL clock

tI2CH

0.6

—

µs

Setup time for a repeated START condition

tI2SVKH

0.6

—

µs

Hold time (repeated) START condition (after this period, the

first clock pulse is generated)

tI2SXKL

0.6

—

µs

Data setup time

tI2DVKH

100

—

Data hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

0 2

—

0.9 3

µs

Set-up time for STOP condition

tI2PVKH

0.6

—

µs

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