MPC8560CPXAPDB datasheet(96/108 Pages) FREESCALE

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

System Design Information

17 System Design Information

This section provides electrical and thermal design recommendations for successful application of the MPC8560.

17.1 System Clocking

The MPC8560 includes three PLLs.

1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency

ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as

described in Section 15.2, “Platform/System PLL Ratio.”

2. The e500 Core PLL generates the core clock as a slave to the platform clock. The frequency ratio between

the e500 core clock and the platform clock is selected using the e500 PLL ratio configuration bits as

described in Section 15.3, “e500 Core PLL Ratio.”

3. The CPM PLL is slaved to the platform clock and is used to generate clocks used internally by the CPM

block. The ratio between the CPM PLL and the platform clock is fixed and not under user control.

17.2 PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1, AVDD2, and

AVDD3, respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages will be

derived directly from VDD through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide three

independent filter circuits as illustrated in Figure 58, one to each of the three AVDD pins. By providing independent

filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It

should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the

recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall,

1993), multiple small capacitors of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled

from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the

periphery of the 783 FC-PBGA footprint, without the inductance of vias.

Figure 58 shows the PLL power supply filter circuit.

Figure 58. PLL Power Supply Filter Circuit

17.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the MPC8560 can generate transient power

surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must

be prevented from reaching other components in the MPC8560 system, and the MPC8560 itself requires a clean,

VDD

AVDD (or L2AVDD)

2.2 µF

GND

Low ESL Surface Mount Capacitors

Ω

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