PSD835G2 datasheet(61/102 Pages) STMICROELECTRONICS

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PSD835G2

MCU I/O Mode

In the MCU I/O mode, the MCU uses the I/O Ports

block to expand its own I/O ports. By setting up the

CSIOP space, the ports on the PSD are mapped

into the MCU address space. The addresses of

the ports are listed in Table 5., page 19.

A port pin can be put into MCU I/O mode by writing

a ’0’ to the corresponding bit in the Control Regis-

ter (Ports E, F and G). The MCU I/O direction may

be changed by writing to the corresponding bit in

the Direction Register, or by the output enable

product term. See Direction Register, page 64.

When the pin is configured as an output, the con-

tent of the Data Out Register drives the pin. When

configured as an input, the MCU can read the port

input through the Data In buffer. See Figure

26., page 60.

Ports A, B and C do not have Control Registers,

and are in MCU I/O mode by default. They can be

used for PLD I/O if they are specified in PSDsoft.

PLD I/O Mode

The PLD I/O Mode uses a port as an input to the

CPLD’s Input Macrocells (IMC), and/or as an out-

put from the CPLD’s Output Macrocells (OMC).

The output can be tri-stated with a control signal.

This output enable control signal can be defined

by a product term from the PLD, or by resetting the

corresponding bit in the Direction Register to '0.'

The corresponding bit in the Direction Register

must not be set to ’1’ if the pin is defined as a PLD

input pin in PSDsoft. The PLD I/O mode is speci-

fied in PSDsoft by declaring the port pins, and then

specifying an equation in PSDsoft.

Address Out Mode

For MCUs with a multiplexed address/data bus,

Address Out Mode can be used to drive latched

addresses on to the port pins. These port pins can,

in turn, drive external devices. Either the output

enable or the corresponding bits of both the Direc-

tion Register and Control Register must be set to

a ’1’ for pins to use Address Out Mode. This must

be done by the MCU at run-time. See Table

37., page 62 for the address output pin assign-

ments on Ports E, F and G for various MCUs.

Note: Do not drive address signals with Address

Out Mode to an external memory device if it is in-

tended for the MCU to Boot from the external de-

vice. The MCU must first Boot from PSD memory

so the Direction and Control register bits can be

set.

Table 35. Port Operating Modes

Note: 1. Can be multiplexed with other I/O functions.

Port Mode

Port A

Port B

Port C

Port D

Port E

Port F

Port G

MCU I/O

Yes

PLD I/O

McellA Outputs

McellB Outputs

Additional Ext. CS Outputs

PLD Inputs

Yes

Address Out

Yes (A7-A0)

or (A15-A8)

Address In

Yes

Data Port

Yes

Peripheral I/O

Yes

JTAG ISP

Yes1

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