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PSD835G2 Arkusz danych(PDF) 96 Page - STMicroelectronics |
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PSD835G2 Arkusz danych(HTML) 96 Page - STMicroelectronics |
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96 / 102 page  PSD835G2 96/102 Figure 49. ISC Timing Table 70. ISC Timing Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only. Symbol Parameter Conditions -70 -90 Unit Min Max Min Max tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) 20 18 MHz tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 23 26 ns tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 23 26 ns tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 22 MHz tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 240 240 ns tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 240 240 ns tISCPSU ISC Port Set Up Time 6 8 ns tISCPH ISC Port Hold Up Time 5 5 ns tISCPCO ISC Port Clock to Output 21 23 ns tISCPZV ISC Port High-Impedance to Valid Output 21 23 ns tISCPVZ ISC Port Valid Output to High-Impedance 21 23 ns ISCCH TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO t ISCCL t ISCPH t ISCPSU t ISCPVZ t ISCPZV t ISCPCO t AI02865 |
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