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WM8734 Arkusz danych(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8734 Arkusz danych(HTML) 11 Page - Wolfson Microelectronics plc |
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11 / 46 page ![]() WM8734 Production Data w PD Rev 4.1 November 2006 11 MASTER CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 1 System Clock Timing Requirements Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high TXTIH 18 ns MCLK System clock pulse width low TXTIL 18 ns MCLK System clock cycle time TXTIY 54 ns MCLK Duty cycle 40:60 60:40 DIGITAL AUDIO INTERFACE – MASTER MODE BCLK ADCDAT ADCLRC DACDAT DACLRC WM8734 CODEC DSP ENCODER/ DECODER Figure 2 Master Mode Connection |
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