LP87702 datasheet(34/99 Pages) TI

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ramp below 800 µs to avoid PGx triggering at start-up. In addition, the PGx is inactive when the invalid input

voltage at VANA, VMON1, or VMON2 pin is detected.

Detected fault sets the corresponding fault bit in PG0_FAULT or in PG1_FAULT register. The detected fault must

be cleared to continue the PGx monitoring. The over-voltage and thermal faults are cleared by writing 1 to the

corresponding interrupt bits in INT_TOP_1 register. Converter, VMONx and VANA faults are cleared by writing 1

to the corresponding register bit in INT_BUCK, INT_BOOST, and INT_DIAG register, respectively. An example

of the PGx pin operation in gated mode is shown in Figure 8-10 and the different use cases for the PGx signal

operation are summarized in Table 8-6.

V(VANA)

VANA_UVLO

State

Shut

down

Read

OTP

Standby

PGx pin

VOUT (Buck1)

VOUT (Boost)

Powergood (Buck1)

Powergood (Boost)

Active

800us Timer

EN (Buck1)

800us Timer

EN (Boost)

4ms

2ms

Clear fault

Figure 8-10. PGx Pin Operation in Gated Mode.

8.3.10.3.2 PGx Pin Operation in Continuous Mode

In this mode the PGx signal shows the validity of the requested voltages continuously. Mode is selected by

setting the PGx_MODE bit to 1 in the PG_CTRL register.

For the continuous mode of operation, the PGx behaves as follows:

• PGx is set to active or asserted state upon exiting the OTP configuration as an initial default state.

• PGx is set to inactive or de-asserted as soon as the converter is enabled.

• PGx status begins indicating the output voltage regulation status immediately and continuously.

• PGx state changes between inactive or deasserted and active or asserted during power-up sequencing

and requested voltage changes, depending on the output voltages being outside or inside of the regualtion

ranges.

When an invalid output voltage of monitored converter is detected, the corresponding bit in the PG0_FAULT

or PG1_FAULT register is set to 1 and the PGx signal becomes inactive. The PG0_FAULT and PG1_FAULT

The PGx signal also indicates the interrupts from VANA, VMON1, and VMON2 inputs and thermal warning and

shutdown. All are cleared by clearing the interrupt bits.

The PGx signal is set inactive when the converter voltage is transitioning from one target voltage to another.

LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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