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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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LP87702 Arkusz danych(PDF) 20 Page - Texas Instruments |
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LP87702 Arkusz danych(HTML) 20 Page - Texas Instruments |
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20 / 99 page  Frequency Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum architecture of the LP87702-Q1 spreads that energy over a large bandwidth. Figure 8-2. Spread Spectrum Modulation 8.3.4 Sync Clock Functionality The LP87702-Q1 device contains a CLKIN input to synchronize buck and boost converters' switching clock with the external clock. Figure 8-3 shows the block diagram of the clocking and PLL module. Table 8-2 shows how the external clock is selected and interrupt is generated depending on the EN_PLL bit in PLL_CTRL register and the external clock availability. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL register and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–30%/+10%) for valid clock detection. The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases the external clock is expected but it is not available. These cases are Startup (Read OTP-to-standby transition) when EN_PLL = 1 and buck or boost converter is enabled (standby-to-active transition) when EN_PLL = 1. 24 MHz RC Oscillator CLKIN Divider ´(;7 _CLK _)5(4´ PLL Divider 24 CLKIN Detector Clock Select Logic Internal 24 MHz clock 1 MHz 1 MHz ´(1 _3//´ 24 MHz Figure 8-3. Clock and PLL Module LP87702-Q1 SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021 www.ti.com 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702-Q1 |
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