USB97C102 datasheet(6/80 Pages) SMSC

6 / 80 page

SMSC DS – USB97C102

Page 6

Rev. 03/23/2000

QFP PIN

NUMBER

SYMBOL

PIN DESCRIPTION

BUFFER

TYPE

XTAL1/

Clock In

24MHz Crystal or clock input.

This pin can be connected to one terminal of the crystal or can be

connected to an external clock when a crystal is not used.

ICLKx

XTAL2

24MHz Crystal

This is the other terminal of the crystal.

OCLKx

EXTCLK

Alternate clock to 8237

An external clock can be used for the internal 8237. This clock can be

used to synchronize the 8237 to other devices.

ICLK

CLKOUT

Clock output.

This clock frequency is the same as the 8051 running clock.

This clock is stopped when the 8051 is stopped. Peripherals should not

use this clock when they are expected to run when the 8051 is stopped.

This clock can be used to synchronize other devices to the 8051.

USB INTERFACE

87, 86

USBD-

USBD+

USB Upstream Connection signals

These are two point-to-point signals and driven differentially.

IOUSB

96, 94, 92,

90.

nPWREN[5:2]

USB Power Enable

A low signal on this pin applies power to the associated USB port (port

#5 through #2). This output signal is active low.

O24

95, 93, 91,

89.

nPWROK[5:2]

USB Over-Current Sense

Input to indicate an over-current condition for a bus powered USB

device on an external downstream port (port #5 through #2).

85, 84, 83,

82, 81, 78,

79, 77.

nPD+[5:2],

nPD -[5:2]

USB Downstream Connection Signals

These are two point-to-point signals and driven differentially. They are

used as standard “Walk Up” USB Port Connections

IOUSB

FLASH INTERFACE

45-52

FD[7:0]

Flash ROM Data Bus

These signals are used to transfer data between 8051 and the external

FLASH.

IO8

75, 74, 68,

65, 64, 69,

70, 63, 73,

43, 72, 71,

62-58,

56-54

FA[19:0]

Flash ROM Address Bus

These signals address memory locations within the FLASH.

NFRD

Flash ROM Read; active low

NFWR

Flash ROM Write; active low

nFCE

Flash ROM Chip Select; active low

FALE

Flash ROM address latch enable

POWER SIGNALS

25,57,76,

101,121

VCC

+3.3 Volt Power

8, 20, 32, 53,

67, 80, 88,

97, 116

GND

Ground Reference

MISCELLANEOUS

41-34

GPIO[7:0]

General Purpose I/O.

These pins can be configured as inputs or outputs under software

control.

I/O24

PWRGD

Active high input.

This signal is used to indicate to that chip that a good power level has

been reached. When inactive/low, all pins are Tri-stated except

TST_OUT and a POR is generated.

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