PCD5002 datasheet(17/48 Pages) PHILIPS

17 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

8.22

Battery condition input

A logic signal from an external sense circuit, signalling

battery condition, can be applied to the BAT input. This

input is sampled each time the receiver is disabled

(RXE

↓ 0).

When enabled via the control register (D2 = 0), the

condition of input BAT is reflected in bit D6 of the status

interrupt at output INT.

When using the UAA2080 pager receiver a battery-low

condition corresponds to a logic HIGH level. With a

different sense circuit the reverse polarity can be used as

well, because every change of state is signalled to an

external controller.

After a reset the initial condition of the battery-low indicator

in the status register is zero.

Table 14 Receiver and oscillator establishment times

(note 1)

Note

1. The exact values may differ slightly from the above

values, depending on the bit rate (see Table 25).

8.23

Synthesizer control

Control of an external frequency synthesizer is possible

via a dedicated 3-line serial interface (outputs ZSD, ZSC

and ZLE). This interface is common to a number of

available synthesizers. The synthesizer is enabled using

the oscillator enable output ROE.

The frequency parameters must be programmed in

EEPROM. Two blocks of maximum 24 bits each can be

stored. Any unused bits must be programmed at the

beginning of a block: only the last bits are used by the

synthesizer.

When the function is selected by SPF programming

(SPF byte 01, bit D6), data is transferred to the

synthesizer each time the PCD5002 is switched from the

OFF to the ON status. Transfer takes place serially in two

blocks, starting with bit 0 (MSB) of block 1 (see Table 28).

Data bits on ZSD change on the falling edges of ZSC. After

clocking all bits into the synthesizer, a latch enable pulse

CONTROL

OUTPUT

ESTABLISHMENT TIME

UNIT

RXE

101530

ROE

copies the data to the internal divider registers. A timing

diagram is illustrated in Fig.6.

The data output timing is synchronous, but has a pause in

the bitstream of each block. This pause occurs in the

13th bit while ZSC is LOW. The nominal pause duration tp

depends on the programmed bit rate for data reception

and is shown in Table 15. The total duration of the 13th bit

is given by tZCL +tp.

A similar pause occurs between the first and the second

data block. The delay between the first latch enable pulse

and the second data block is given by tZDL2 +tp.

The complete start-up timing of the synthesizer interface is

illustrated in Fig.13.

Table 15 Synthesizer programming pause

8.24

Serial microcontroller interface

The PCD5002 has an I2C-bus serial microcontroller

interface capable of operating at 400 kbits/s.

The PCD5002 is a slave transceiver with a 7-bit I2C-bus

address 39 (bits A6 to A0 = 0100111).

Data transmission requires 2 lines: SDA (data) and SCL

(clock), each with an external pull-up resistor. The clock

signal (SCL) for any data transmission must be generated

by the external controlling device.

A transmission is initiated by a START condition

(S: SCL = 1, SDA =

↓) and terminated by a STOP

condition (P: SCL = 1, SDA =

↑).

Data bits must be stable when SCL is HIGH. If there are

multiple transmissions, the STOP condition can be

replaced with a new START condition.

Data is transferred on a byte basis, starting with a device

address and a read/write indicator. Each transmitted byte

must be followed by an acknowledge bit A (active LOW).

If a receiving device is not ready to accept the next

complete byte, it can force a bus wait state by holding SCL

LOW.

The general I2C-bus transmission format is illustrated in

Fig.7. Formats for master/slave communication are

illustrated in Fig.8.

BIT RATE (bit/s)

tp (clocks)

tp (µs)

512

119

1549

1200

430

2400

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