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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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PCD5002 Arkusz danych(PDF) 38 Page - NXP Semiconductors |
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PCD5002 Arkusz danych(HTML) 38 Page - NXP Semiconductors |
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38 / 48 page  1997 Jun 24 38 Philips Semiconductors Product specification Advanced POCSAG and APOC-1 Paging Decoder PCD5002 Receiver control tRXT RXE and ROE transition time CL =5pF − 100 − ns tRXON RXE establishment time (nominal values: actual duration is bit rate dependent, see Table 25) SPF byte 01H; bits: D1, D0 = 0 0 − 5 − ms D1, D0 = 0 1 − 10 − ms D1, D0 = 1 0 − 15 − ms D1, D0 = 1 1 − 30 − ms tROON ROE establishment time (nominal values: actual duration is bit rate dependent, see Table 25) SPF byte 01H; bits: D3, D2 = 0 0 − 20 − ms D3, D2 = 0 1 − 30 − ms D3, D2 = 1 0 − 40 − ms D3, D2 = 1 1 − 50 − ms I2C-bus interface fSCL SCL clock frequency 0 − 100 kHz tLOW SCL clock low period 4.7 −−µs tHIGH SCL clock HIGH period 4.0 −−µs tSU;DAT data set-up time 250 −− ns tHD;DAT data hold time 500 −− ns tr SDA and SCL rise time −− 1000 ns tf SDA and SCL fall time −− 300 ns CB capacitive bus line load −− 400 pF tSU;STA START condition set-up time 4.7 −−µs tHD;STA START condition hold time 4.0 −−µs tSU;STO STOP condition set-up time 4.0 −−µs Reset tRST external reset duration 50 −−µs tRSU set-up time after reset oscillator running −− 105 µs tOSU set-up time after switch-on oscillator running −− 4ms Data input tTDI data input transition time see Fig.14 −− 100 µs tDI1 data input logic 1 duration see Fig.14 tBIT −∞ tDI0 data input logic 0 duration see Fig.14 tBIT −∞ POCSAG data timing (512 bits/s) fDI data input rate SPF byte 01H; D5 = 0; D4 = 0 − 512 − bits/s tBIT bit duration − 1.9531 − ms tCW codeword duration − 62.5 − ms tPA preamble duration 1125 −− ms tBAT batch duration − 1062.5 − ms SYMBOLS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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