PCD5002 datasheet(29/48 Pages) PHILIPS

29 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

Table 25 Establishment time as a function of bit rate

Table 26 Special programmed functions (EEPROM address 02H)

Table 27 Special programmed functions (EEPROM address 03H)

NOMINAL

ESTABLISHMENT

TIME

ACTUAL ESTABLISHMENT TIME

512 (bits/s)

1024 (bits/s)

1200 (bits/s)

2400 (bits/s)

5 ms

5.9 ms (3 bits)

5.9 ms (6 bits)

5 ms (6 bits)

5 ms (12 bits)

10 ms

11.7 ms (6 bits)

11.7 ms (12 bits)

10 ms (12 bits)

10 ms (24 bits)

15 ms

15.6 ms (8 bits)

15.6 ms (16 bits)

16.7 ms (20 bits)

16.7 ms (40 bits)

20 ms

23.4 ms (12 bits)

23.4 ms (24 bits)

20 ms (24 bits)

20 ms (48 bits)

30 ms

31.2 ms (16 bits)

31.2 ms (32 bits)

26.7 ms (32 bits)

26.7 ms (64 bits)

40 ms

39.1 ms (20 bits)

39.1 ms (40 bits)

40 ms (48 bits)

40 ms (96 bits)

50 ms

46.9 ms (24 bits)

46.9 ms (48 bits)

53.3 ms (64 bits)

53.3 ms (128 bits)

BIT (MSB: D7)

VALUE

DESCRIPTION

not used

D3 and D2

0 0

32768 Hz real time clock reference

0 1

50 Hz square wave

1 0

2 Hz

1 1

⁄60 Hz

signal test mode enabled (REF and INT outputs)

burst error correction enabled

D7 and D6

30 s (+ 0.5 s max.) transmitter off time-out

60 s (+ 1 s max.)

120 s (+ 2 s max.)

240 s (+ 4 s max.)

BIT (MSB: D7)

VALUE

DESCRIPTION

D1 and D0

0 0

2048 Hz acoustic alerter frequency

0 1

2731 Hz

1 0

4096 Hz

1 1

3200 Hz

automatic POCSAG alert generation enabled

not used

INT output polarity: active LOW

INT output polarity: active HIGH

not used

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