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DSP56362P Arkusz danych(PDF) 93 Page - Freescale Semiconductor, Inc |
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DSP56362P Arkusz danych(HTML) 93 Page - Freescale Semiconductor, Inc |
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93 / 152 page ![]() Digital Audio Transmitter Timing DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-67 Figure 3-43 ESAI HCKR Timing 3.15 Digital Audio Transmitter Timing Figure 3-44 Digital Audio Transmitter Timing Table 3-25 Digital Audio Transmitter Timing No. Characteristic Expression 100 MHz Unit Min Max ACI frequency1 1 In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56362 internal clock frequency. For example, if the DSP56362 is running at 100 MHz internally, the ACI frequency should be less than 50 MHz. —— 50 MHz 220 ACI period 2 × T C 20 — ns 221 ACI high duration 0.5 × T C 5— ns 222 ACI low duration 0.5 × T C 5— ns 223 ACI rising edge to ADO valid 1.5 × T C —15 ns HCKR SCKR (output) 465 463 ACI ADO 220 223 AA1280 221 222 |
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