MPC8250VR datasheet(2/60 Pages) FREESCALE

2 / 60 page

MPC8250 Hardware Specifications, Rev. 1

Freescale Semiconductor

Features

Figure 1 shows the block diagram for the MPC8250.

Figure 1. MPC8250 Block Diagram

Features

The major features of the MPC8250 are as follows:

•

Footprint-compatible with the MPC8260

•

Dual-issue integer core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 150–200 MHz

— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— PowerPC architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at

200 MHz)

16 Kbytes

G2 Core

I-Cache

I-MMU

16 Kbytes

D-Cache

D-MMU

Communication Processor Module (CPM)

Timers

Parallel I/O

Baud Rate

Generators

32 Kbytes

32-bit RISC Microcontroller

and Program ROM

Serial

DMAs

4 Virtual

IDMAs

60x-to-PCI

Bridge

Memory Controller

Clock Counter

System Functions

System Interface Unit

(SIU)

Local Bus

32 bits, up to 66 MHz

PCI Bus

32 bits, up to 66 MHz

MCC2

FCC1

FCC2

FCC3

SCC1

SCC2

SCC3

SCC4

SMC1

SMC2

SPI

I2C

Serial Interface

3 MII

Ports

60x Bus

Dual-Port RAM

Interrupt

Controller

Time Slot Assigner

4 TDM Ports

Non-Multiplexed

I/O

60x-to-Local

Bus Interface Unit

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