Data Sheet

ADRF5162

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 10 of 11

The ADRF5162 has two power supply pins (VDD and VSS) and one

control pin (CTRL). Figure 14 shows the external components and

connections for supply and control pins.

The VDD and VSS pins are decoupled with 100 pF and 0.1 μF

multilayer ceramic capacitors, respectively, while the control pin is

decoupled with a 100 pF multilayer ceramic capacitor. The device

pinout allows the placement of the decoupling capacitors close to

the device. No other external components are needed for bias and

operation, except DC blocking capacitors on the RF pins when the

RF lines are biased at a voltage different than 0 V. For more details,

see the Pin Configuration and Function Descriptions section.

Figure 14. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50 Ω internally and the pinout is

designed to mate a coplanar waveguide (CPWG) with 50 Ω charac-

teristic impedance on the PCB. Figure 15 shows the referenced

CPWG RF trace design for an RF substrate with 10 mil thick

Rogers RO4350 dielectric material. RF trace with 18 mil width

and 13 mil clearance is recommended for 2.8 mil finished copper

thickness.

Figure 15. Example PCB Stack-Up

Figure 16 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with as

many filled, through vias as allowed for optimal RF, and thermal

performance. The primary thermal path for the device is the bottom

side. Therefore, a heatsink is required underneath the PCB to

ensure maximum heat dissipation and to reduce thermal rise on the

PCB during high-power applications.

Figure 16. PCB Routings

Figure 17 shows the recommended layout from the device RF pins

to the 50 Ω CPWG on the referenced stack-up. PCB pads are

drawn 1:1 to device pads. The ground pads are drawn soldermask

defined and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended with the same width and

tapered to RF trace. The paste mask is also designed to match

the pad without any aperture reduction. The paste is divided into

multiple openings for the paddle.

Figure 17. Recommended RF Pin Transitions

For alternate PCB stack-ups with different dielectric thickness and

CPWG design, and for further recommendations, contact Analog

Devices Technical Support.