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ISO7421 Arkusz danych(PDF) 12 Page - Texas Instruments |
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ISO7421 Arkusz danych(HTML) 12 Page - Texas Instruments |
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12 / 25 page ![]() Case Temperature − C ° 0 20 40 60 80 100 120 140 160 180 0 50 100 150 200 G002 VCC1, VCC2 at 3.45 V VCC1, VCC2 at 5.25 V ISO7421-EP SLLSEN3 – DECEMBER 2015 www.ti.com SPACER NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 8.3.3 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RθJA = 212°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C 112 Safety input, output, or supply IS mA current RθJA = 212°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C 171 TS Maximum safety temperature 150 °C The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Figure 10. RθJC Thermal Derating Curve per VDE 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7421-EP |
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