TMS320VC33 datasheet(35/53 Pages) TI2

35 / 53 page

30 Ω

15 kΩ

SHZ

Bus Keeper

Internal

Data Bus

R/ W

External Data

Bus Pin

SM320VC33, SMJ320VC33

www.ti.com

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

Table 5. MUX Select (Bus Control Register Bits 4 and 3)

BIT 4

BIT 3

RESULTS

Ignore internal wait counter and use only external READY

Use only internal wait counter and ignore ready pin

Logical AND internal wait counter with ready pin

Logical OR internal wait counter with ready pin (reset default)

8.2.10 Posted Writes

External writes are effectively “posted” to the bus, which then acts like an output latch until the write completes.

Therefore, if the application code is executing internally, it can perform a very-slow external write with no penalty

because the bus acts like it has a one-level-deep write FIFO.

8.2.11 Data Bus I/O Buffer

The circuit shown in Figure 30 is incorporated into each data pin to lightly “hold” the last driven value on the data

bus pins when the DSP or an external device is not actively driving the bus. Each bus keeper is built from a

three-state driver with nominal 15-k

Ω output resistance which is fed back to the input in a positive feedback

configuration. The resistance-isolated driver then pulls the output in one direction or the other keeping the last

driven value. This circuit is enabled in all functional modes and is only disabled when SHZ is pulled low.

Figure 30. Bus Keeper Circuit

For an external device to change the state of these pins, it must be able to drive a small dc current until the

driver threshold is crossed. At the crossover point, the driver changes state, agreeing with the external driver and

assisting the change. The voltage threshold of the bus keeper is approximately at 50% of the DVDD supply

voltage. The typical output impedance of 30

Ω for all SMx320VC33 I/O pins is easily capable of meeting this

requirement.

8.2.12 Bootloader Operation

When MCBL/MP = 1, an internal ROM is decoded into the address range of 0x000000 to 0x000FFF. Therefore,

when reset occurs, execution begins within the internal ROM program and vector space. No external activity is

evident until one of the boot options is enabled. These options are enabled by pulling an external interrupt pin

low, which the boot-load software then detects, causing a particular routine to be executed (see Table 6).

Table 6. INT0 to INT3 Sources

ADDRESS/SOURCE WHERE BOOT

ACTIVE INTERRUPT

DATA FORMAT

DATA IS READ FROM

INT0

0x001000

8-, 16-, or 32-bit width

INT1

0x400000

8-, 16-, or 32-bit width

INT2

0xFFF000

8-, 16-, or 32-bit width

INT3

Serial port

32-bit, external clock, and frame synch

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