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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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IS25LE512M-RMLA3:P-TY Arkusz danych(PDF) 27 Page - Integrated Silicon Solution, Inc |
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IS25LE512M-RMLA3:P-TY Arkusz danych(HTML) 27 Page - Integrated Silicon Solution, Inc |
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27 / 189 page  IS25LE512M IS25WE512M Integrated Silicon Solution, Inc.- www.issi.com 27 Rev. A6 06/16/2025 6.2 FUNCTION REGISTER Function Register Format and Bit definition are described in Table 6.5 and Table 6.6. Table 6.5 Function Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRL3 IRL2 IRL1 IRL0 ESUS PSUS TBS Dedicated RESET# Disable Default 0 0 0 0 0 0 0 0 or 1 Table 6.6 Function Register Bit Definition Bit Name Definition Read /Write Type Bit 0 Dedicated RESET# Disable Dedicated RESET# Disable bit “0” indicates Dedicated RESET# was enabled “1” indicates Dedicated RESET# was disabled R/W for 0 R only for 1 OTP Bit 1 TBS Top/Bottom Selection. (See Table 6.4 for details) “0” indicates Top area. “1” indicates Bottom area. R/W OTP Bit 2 PSUS Program suspend bit: “0” indicates program is not suspend “1” indicates program is suspend R Volatile Bit 3 ESUS Erase suspend bit: "0" indicates Erase is not suspend "1" indicates Erase is suspend R Volatile Bit 4 IR Lock 0 Lock the Information Row 0: “0” indicates the Information Row can be programmed “1” indicates the Information Row cannot be programmed R/W OTP Bit 5 IR Lock 1 Lock the Information Row 1: “0” indicates the Information Row can be programmed “1” indicates the Information Row cannot be programmed R/W OTP Bit 6 IR Lock 2 Lock the Information Row 2: “0” indicates the Information Row can be programmed “1” indicates the Information Row cannot be programmed R/W OTP Bit 7 IR Lock 3 Lock the Information Row 3: “0” indicates the Information Row can be programmed “1” indicates the Information Row cannot be programmed R/W OTP Note: Once OTP bits of Function Register are written to “1”, it cannot be modified to “0” any more. Dedicated RESET# Disable bit: The default status of the bit is dependent on package type. The device with dedicated RESET# (16-pin SOIC and 24-ball BGA) can be programmed to “1” to disable dedicated RESET# function to move RESET# function to Hold#/RESET# pin (or ball). So the device with dedicated RESET# can be used for dedicated RESET# application and HOLD#/RESET# application. TBS bit: BP0~3 area assignment can be changed from Top (default) to Bottom by setting TBS bit to “1”. However, once Bottom is selected, it cannot be changed back to Top since TBS bit is OTP. See Table 6.4 for details. PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The PSUS changes to “1” after a suspend command is issued during the program operation. Once the suspended Program resumes, the PSUS bit is reset to “0”. ESUS bit: The Erase Suspend Status bit indicates when an Erase operation has been suspended. The ESUS bit is “1” after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the ESUS bit is reset to “0”. |
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