Data Sheet

ADRF5703

THEORY OF OPERATION

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Rev. 0 | 15 of 19

The ADRF5703 incorporates a 7-bit fixed attenuator array that of-

fers an attenuation range of 31.75dB in 0.25dB steps. An integrated

driver provides serial or parallel mode control of the attenuator

array.

The ADRF5703 has nine digital control inputs, D0 (LSB) to D6

(MSB), LE, and PS. To select the desired attenuation state in serial

or parallel mode, refer to Table 8 and Table 9. For the timing

diagrams, see Figure 35, Figure 36, and Figure 37.

POWER SUPPLY

The ADRF5703 requires a positive supply voltage applied to the

VDD pin and a negative supply applied to the VSS pin. Bypassing

capacitors are recommended on the supply line to filter high fre-

quency noise.

The power-up sequence is as follows:

1. Connect GND to ground.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3. Power up the digital control inputs. The order of the digital

control inputs is not important. However, powering the digital

control inputs before the VDD voltage supply can inadvertently

forward bias and damage the internal ESD structures. To avoid

this damage, use a series 1kΩ resistor to limit the current

flowing into the digital control input pins in such cases.

4. Apply an RF input signal to ATTIN or ATTOUT.

The power-down sequence is the reverse order of the power-up

sequence.

Power-Up State

The ADRF5703 has internal power-on reset circuitry that sets the

attenuator to the maximum attenuation state (31.75dB) when VDD

is applied.

SINGLE-SUPPLY OPERATION

The ADRF5703 can operate with a single positive supply voltage

applied to the VDD pin and the VSS pin connected to ground. In

single-supply operation, the switching characteristics, linearity, and

power handling performance are derated, see Table 2 for additional

information.

RF INPUT AND OUTPUT

Both RF ports (ATTIN and ATTOUT) are DC-coupled to 0V. No DC

blocking is required at the RF ports when the RF line potential is

equal to 0V.

The power handling is defined by the ATTIN port. Refer to the RF

input power specifications in Table 1.

Table 8. Truth Table

Digital Control Input1

Attenuation State (dB)

D6

D5

D4

D3

D2

D1

D0

Low

Low

Low

Low

Low

Low

Low

0 (reference)

Low

Low

Low

Low

Low

Low

High

0.25

Low

Low

Low

Low

Low

High

Low

0.5

Low

Low

Low

Low

High

Low

Low

1.0

Low

Low

Low

High

Low

Low

Low

2.0

Low

Low

High

Low

Low

Low

Low

4.0

Low

High

Low

Low

Low

Low

Low

8.0

High

Low

Low

Low

Low

Low

Low

16.0

High

High

High

High

High

High

High

31.75

1 Any combination of the attenuation states within this table provides an attenuation equal to the sum of bits selected.

Figure 34. Simplified Circuit Diagram