Data Sheet

ADRF5703

THEORY OF OPERATION

analog.com

Rev. 0 | 16 of 19

SERIAL OR PARALLEL MODE SELECTION

The ADRF5703 can be controlled in either serial or parallel mode

by setting the PS pin to high or low, respectively (see Table 9).

Table 9. Mode Selection

PS

Control Mode

Low

Parallel

High

Serial

SERIAL MODE INTERFACE

The ADRF5703 supports a 4-wire SPI: serial data input (SERIN),

clock (CLK), serial data output (SEROUT), and latch enable (LE).

The serial control interface is activated when PS pin is set to high.

The ADRF5703 attenuation states can be controlled using the 7-bit

or 8-bit SERIN data. If an 8-bit word is used to control the state of

the attenuator, the first two bits are don't care bit. It does not matter

if these bits are held low or high, or if they are omitted altogether.

Only Bits[D6:D0] set the state of the attenuator.

In serial mode, the SERIN data is clocked MSB first on the rising

CLK edges into the shift register. Then, LE must be toggled high to

latch the new attenuation state into the device. LE must be set to

low to clock new SERIN data into the shift register because CLK is

masked to prevent the attenuator value from changing if LE is kept

high. See Figure 35, Figure 36, the Timing Specifications section,

and the RF Input and Output section for additional information.

Figure 35. Serial Control Timing Diagram

Figure 36. Serial Output Timing Diagram