ADRF5703BCCZN-R7 datasheet(18/19 Pages) AD

18 / 19 page

Data Sheet

ADRF5703

APPLICATIONS INFORMATION

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Rev. 0 | 18 of 19

The ADRF5703 has two power supply pins (VDD and VSS) and

nine control pins (PS, LE, D0 to D6). Figure 38 shows the external

components and connections for the supply and control pins. The

supply pins (VDD and VSS) are decoupled with 0.1μF multilayer

ceramic capacitor. Place the decoupling capacitor as close as

possible to the ADRF5703. The device pinout allows the placement

of the decoupling capacitors close to the ADRF5703. No other

external components are required for bias and operation, except

DC blocking capacitors on the RF pins (ATTIN and ATTOUT) when

the RF lines are biased at a voltage different than 0V. Refer to

Pin Configuration and Function Descriptions section for additional

information.

Figure 38. Simplified Application Circuit

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50Ω internally, and the pinout is

designed to mate a coplanar waveguide (CPWG) with a 50Ω char-

acteristic impedance on the PCB. Figure 39 shows the referenced

CPWG RF trace design for an RF substrate with an 8mil thick

Rogers RO4003 dielectric material. The RF trace with a 14mil width

and a 7mil clearance is recommended for 1.5mil finished copper

thickness.

Figure 39. Example PCB Stackup

Figure 40 shows the routing of the RF traces, supply, and control

signals from the ADRF5703. The ground planes are connected with

as many filled through vias as allowed for optimal RF and thermal

performance. The primary thermal path for the device is the bottom

side.

Figure 40. PCB Routings

Figure 41 shows the recommended layout from the ATTIN and ATT-

OUT pins of the ADRF5703 to the 50Ω CPWG on the referenced

stackup. PCB pads are drawn 1:1 to device pads. The ground pads

are drawn solder mask defined, and the signal pads are drawn as

pad defined. The RF trace from the PCB pad is extended to the

device edge and tapered to the RF trace with a 45° angle. The

paste mask is also designed to match the pad without any aperture

reduction and is divided into multiple openings for the paddle.

Figure 41. Recommended ATTIN Pin and ATTOUT Pin Transitions

For alternate PCB stackups with different dielectric thickness and

CPWG design, contact Analog Devices, Inc., Technical Support

Request for further recommendations.

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