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M25P10 Arkusz danych(PDF) 10 Page - STMicroelectronics |
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M25P10 Arkusz danych(HTML) 10 Page - STMicroelectronics |
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10 / 21 page ![]() M25P10 10/21 the device once the Hardware Protected Mode is entered. The timing sequence is shown in Figure 10. Sector Erase (SE) Prior to any Sector Erase attempt, a write enable instruction (WREN) must have been previously sent (the S input driven low, WREN instruction properly transmitted and the S input driven high). After the WREN instruction decoding, the memory sets the Write Enable Latch (WEL) which allows the execution of any further Sector Erase. The Sector Erase instruction is entered by driving the Chip select input (S) low, followed by the instruction byte and 3 address bytes on Data In input (D). Any address of the Sector (see Table 4) is a valid address for the Sector Erase instruction. The Chip Select input (S) must be driven low for the entire duration of the sequence. The device must be deselected just after the eighth bit of the last address byte has been latched in. If not, the Sector Erase instruction is not executed. As soon as the device is deselected, the self-timed Sector Erase cycle (tSE) is initiated. While the Sector Erase cycle is in progress, the status register may be read to check the WIP bit value. WIP is high during the self-timed Sector Erase cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. A Sector Erase instruction applied to a Sector which is software protected by the BPi bits (see Table 4 and Table 5) is not initiated. The timing sequence is shown in Figure 13. Bulk Erase (BE) Prior to any Bulk Erase attempt, a write enable instruction (WREN) must have been previously sent (the S input driven low, WREN instruction properly transmitted and the S input driven high). After the WREN instruction decoding, the memory Figure 13. SE: Sector Erase Sequence Note: 1. Address bits A23 to A17 are Don’t Care on the M25P10 series. 24 BIT ADDRESS C D AI03751 S 2 1 3456789 29 30 31 INSTRUCTION 0 23 22 2 0 1 MSB Figure 14. BE: Bulk Erase Sequence C D AI03752 S 2 1 34567 0 INSTRUCTION |
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