M25P10 datasheet(13/21 Pages) STMICROELECTRONICS

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M25P10

– The device is in the low power standby state

(not the Deep Power Down Mode).

– The chip is deselected.

– The Write Enable Latch is reset.

POWER UP OPERATION

In order to prevent data corruption and inadvertent

Page Program, Erase or Write Status Register

operations, an internal VCC comparator inhibits all

these features if the VCC voltage is lower than VWI

(see Table 8).

Once the voltage applied on the VCC pin goes over

the VWI threshold (VCC>VWI):

– Page Program, Erase and Write Status Register

operations are allowed after a time-out of tPUW,

as specified in Table 8.

– This time-out delay allows the voltage applied

on VCC pin to reach VCC(min) of the device. It

should be noted that none of the device's

operation are guaranteed till VCC is not ≥

VCC(min).

DATA PROTECTION AND PROTOCOL

CONTROL

Once all bits of a Page Program, Sector Erase,

Bulk Erase or Status Register Write instruction are

received; the S input must be driven high

(Deselect) right after the proper clock count in

order to execute the instruction, that is the Chip

Select S must driven high after a clock pulses

count multiple of 8 bit.

Attempting to access the memory array during a

Write, Program or Erase cycle is ignored, however

the internal cycle continues.

ELECTRONIC SIGNATURE

The device features an 8 bits Electronic Signature

(10h) which can be read with the help of the RES

instruction

(please

see

the

section

entitled

“Release from Deep Power Down Mode and Read

Electronic Signature (RES)” on page 12).

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set at ’1’ (each byte = FFh). The

Status Register content is 00h (all Status Register

bits are ’0’).

Table 9. Initial Status Register Format

000

Table 8. Power-Up Timing and VWI Threshold

(TA = –40 to 85 °C)

Note: 1. These parameters are characterized only.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

IVSL1

VCC(min) to S low

µs

IPUW1

Time delay to Write operation

VWI1

Write Inhibit Voltage

1.5

2.5

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