RZSLASHA3M datasheet(14/53 Pages) RENESAS

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RZ/A3M Group Datasheet

Section 3. Electrical Characteristics

R01DS0482EJ0110

Rev.1.10

Page 14 of 53

Mar 31, 2025

3.3

Power-On/Power-Off Sequence

VDD (Core)

PLL23/5_DVDD11

DDR_VDDQ1, DDR_VDDQ2

(DDR IO Power)

VDD18

DSI_VDD18

OTP_VDD18

PLL1/23/4/5_AVDD18

SD0_PVDD (only 1.8 V using)

SPI_PVDD (1.8 V)

USB_VDD18

PVDD (GPIO 3.3 V)

SD0_PVDD (1.8 V/3.3 V switching*

or only 3.3 V using)

SPI_PVDD (3.3 V)

USB_VDD33

OSC Input

PRST#

1.1 V

3.3 V

1.2/1.35 V

1.8 V

clock

signal

100ms (Max )

After 1.1 V power-on or t he same

clock need to be stable

100ms (Max )

1 µsec (Min)

100ms (Max )

Figure 3.1

Power-On/Power-Off Sequence

NOTES

Turn on 3.3 V after 1.1 V/1.8 V.

Note 1.

About SD0_PVDD, especially in the case of switching between 1.8 V and 3.3 V at same power rail, 1.8-V power-on/off

timing can also follow 3.3-V power rail sequence as shown in the Figure 3.1.

Turn on the DDR IO power supply at the same time as or after the 1.1-V power supply.

From first power rising start to last power rising end must be within 100 ms.

The power-off sequence is the reverse of the power-on sequence

(PRST#

→ Low  3.3 V = OFF  Other = OFF)

PRST# should be changed from Low to High after the 3.3-V power supply is turned on, after 1 µsec, and after the

input clock from the oscillator stabilizes.

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