RZSLASHA3M datasheet(2/53 Pages) RENESAS

2 / 53 page

RZ/A3M Group Datasheet

Section 1. Overview

R01DS0482EJ0110

Rev.1.10

Page 2 of 53

Mar 31, 2025

Section 1 Overview

1.1

Outline of Specification

1.1.1

CPU Core

Item

Description

System CPU Cortex-A55

● Arm Cortex-A55 Single MPCore 1.0 GHz

● L1 I-cache 32 Kbytes (Parity) / D-cache 32 Kbytes (ECC)

● L2 cache 0 Kbyte

● L3 cache 256 Kbytes (ECC)

● Arm® NEON™ / FPU supported

● Arm® v8.2-A architecture

Boot

● 5 boot modes

Boot Mode 3:

Booting from a serial NOR flash memory (Single / Quad)

connected to the SPI Multi I/O bus space (1.8 V)

Boot Mode 4:

Booting from a serial NOR flash memory (Single / Quad)

connected to the SPI Multi I/O bus space (3.3 V)

Boot Mode 5:

Booting from SCIF download

Boot Mode 6:

Booting from a serial NAND flash memory (Single / Quad)

Connected to the SPI Multi I/O bus space (1.8V)

Boot Mode 7:

Booting from a serial NAND flash memory (Single / Quad)

Connected to the SPI Multi I/O bus space (3.3V)

Debug Interface

● Arm® CoreSight™ architecture

● JTAG / SWD interface supported

● ETF 16 Kbytes for program flow trace (each cluster)

RZ/A3M Arkusz danych(PDF) 2 Page - Renesas Technology Corp