RZSLASHA3M datasheet(21/53 Pages) RENESAS

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RZ/A3M Group Datasheet

Section 3. Electrical Characteristics

R01DS0482EJ0110

Rev.1.10

Page 21 of 53

Mar 31, 2025

3.5

AC Characteristics

Conditions:

VDD = PLL23_DVDD11 = PLL5_DVDD11 = 1.1 ± 0.05 V,

PLL1_AVDD18 = PLL23_AVDD18 = PLL4_AVDD18 = 1.8 ± 0.18 V,

VDD18 = JTAG_PVDD = 1.8 ± 0.18 V, OTP_VDD18 = 1.8 V ± 0.15 V,

USB_VDD18 = DSI_VDD18 = 1.8 ± 0.15 V,

PVDD = 3.3 ± 0.33 V, USB_VDD33 = 3.3 ± 0.3 V, DDR_VDDQ = 1.2 ± 0.06 V/1.283 to 1.45 V,

SPI_PVDD = SDn_PVDD (n = 0) = 3.3 ± 0.33 V/1.70 to 1.95 V, VSS = 0 V,

Ta = −40 to +85°C, Tj = −40 to +110°C

3.5.1

Clock Timing

Table 3.15

Clock Timing Table

Item

Symbol

Min.

Max.

Unit

Figures

EXCLK clock input frequency

fEX

– 100ppm

24 + 100ppm

MHz

Figure 3.4

EXCLK clock input cycle time

tEXcyc

41.67

AUDIO_CLK1, AUDIO_CLK2 clock input frequency

(external clock is input)

fEX

MHz

AUDIO_CLK1, AUDIO_CLK2 clock input cycle time

(external clock is input)

tEXcyc

100

EXCLK, AUDIO_CLK1, AUDIO_CLK2

clock input low level pulse width

tEXL

0.4

0.6

tEXcyc

EXCLK, AUDIO_CLK1, AUDIO_CLK2

clock input high level pulse width

tEXH

0.4

0.6

tEXcyc

EXCLK, AUDIO_CLK1, AUDIO_CLK2

clock input rise time

tEXr

—

EXCLK, AUDIO_CLK1, AUDIO_CLK2

clock input fall time

tEXf

—

Oscillator stabilization time

tOSC

—

Figure 3.5, Figure

3.6

Mode hold time

tMDH

—

100

Mode setup time

tMDS

—

100

1/2 PVDD

EXCLK,

AUDIO_CLK1,

AUDIO_CLK2

(input)

tEXcyc

tEXH

tEXL

VIH

VIL

VIH

1/2 PVDD

tEXf

tEXr

Note:

When the clock is input on the EXCLK, AUDIO_CLK1 or AUDIO_CLK2

Figure 3.4

EXCLK, AUDIO_CLK1 and AUDIO_CLK2 Clock Input Timing

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