NRF52810-QFAA-R datasheet(91/483 Pages) NORDIC

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Power and clock management

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

SRC

Source of LFCLK

32.768 kHz RC oscillator

Xtal

32.768 kHz crystal oscillator

Synth

32.768 kHz synthesized from HFCLK

STATE

LFCLK state

NotRunning

LFCLK not running

Running

LFCLK running

5.4.3.7 LFCLKSRCCOPY

Address offset: 0x41C

Copy of LFCLKSRC register, set when LFCLKSTART task was triggered

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

SRC

Clock source

32.768 kHz RC oscillator

Xtal

32.768 kHz crystal oscillator

Synth

32.768 kHz synthesized from HFCLK

5.4.3.8 LFCLKSRC

Address offset: 0x518

Clock source for the LFCLK

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

C B

A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

RW SRC

Clock source

32.768 kHz RC oscillator

Xtal

32.768 kHz crystal oscillator

Synth

32.768 kHz synthesized from HFCLK

RW BYPASS

Enable or disable bypass of LFCLK crystal oscillator with

external clock source

Disabled

Disable (use with Xtal or low-swing external source)

Enabled

Enable (use with rail-to-rail external source)

RW EXTERNAL

Enable or disable external source for LFCLK

Disabled

Disable external source (use with Xtal)

Enabled

Enable use of external source instead of Xtal (SRC needs to

be set to Xtal)

5.4.3.9 CTIV ( Retained )

Address offset: 0x538

This register is a retained register

4430_161 v1.0

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