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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.6 RESET/STOP MANAGER

The Reset/Stop Manager resets the MCU when

one of the three following events occurs:

– A Hardware reset, initiated by a low level on the

Reset pin.

– A Software reset, initiated by a HALT instruction

(when enabled).

– A Watchdog end of count condition.

The Low Voltage Detector (LVD) (see Section 5.8)

generates a reset when:

– the power supply, when rising, is under the LVD

VLVDR Threshold.

– the power supply, when falling, is under the LVD

VLVDF Threshold.

The event which caused the last Reset is flagged

in the CLK_FLAG register, by setting the SOF-

TRES or the WDGRES bits respectively; a hard-

ware initiated reset will leave both these bits reset.

The hardware reset overrides all other conditions

and forces the ST9 to the reset state. During Re-

set, the internal registers are set to their reset val-

ues, where these are defined, and the I/O pins are

set to the Bidirectional Weak Pull-up mode.

Reset is asynchronous: as soon as the reset pin is

driven low, a Reset cycle is initiated.

Figure 37. Oscillator Start-up Sequence and Reset Timing

VDD MAX

VDD MIN

OSCIN

INTCLK

RESET

OSCOUT

5.1 ms (*)

VR02085A

TSTART-UP

TINTCLK

(*) with 4 MHz quartz

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