ST92141 datasheet(35/179 Pages) STMICROELECTRONICS

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ST92141 - DEVICE ARCHITECTURE

MMU REGISTERS (Cont’d)

DATA PAGE REGISTER 0 (DPR0)

R240 - Read/Write

Reset value: undefined

This register is relocated to R224 if EMR2.5 is set.

Bits 7:0 = DPR0_[7:0]: These bits define the 16-

Kbyte Data Memory page number. They are used

as the most significant address bits (A21-14) to ex-

tend the address during a Data Memory access.

The DPR0 register is used when addressing the

virtual address range 0000h-3FFFh.

DATA PAGE REGISTER 1 (DPR1)

R241 - Read/Write

Reset value: undefined

This register is relocated to R225 if EMR2.5 is set.

Bits 7:0 = DPR1_[7:0]: These bits define the 16-

Kbyte Data Memory page number. They are used

as the most significant address bits (A21-14) to ex-

tend the address during a Data Memory access.

The DPR1 register is used when addressing the

virtual address range 4000h-7FFFh.

DATA PAGE REGISTER 2 (DPR2)

R242 - Read/Write

Reset value: undefined

This register is relocated to R226 if EMR2.5 is set.

Bits 7:0 = DPR2_[7:0]: These bits define the 16-

Kbyte Data memory page. They are used as the

most significant address bits (A21-14) to extend

the address during a Data memory access. The

DPR2 register is involved when the virtual address

is in the range 8000h-BFFFh.

DATA PAGE REGISTER 3 (DPR3)

R243 - Read/Write

Reset value: undefined

This register is relocated to R227 if EMR2.5 is set.

Bits 7:0 = DPR3_[7:0]: These bits define the 16-

Kbyte Data memory page. They are used as the

most significant address bits (A21-14) to extend

the address during a Data memory access. The

DPR3 register is involved when the virtual address

is in the range C000h-FFFFh.

DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0

DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0

DPR2_7 DPR2_6 DPR2_5 DPR2_4 DPR2_3 DPR2_2 DPR2_1 DPR2_0

DPR3_7 DPR3_6 DPR3_5 DPR3_4 DPR3_3 DPR3_2 DPR3_1 DPR3_0

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